`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2021/03/29 12:22:05
// Design Name: 
// Module Name: instr_ram
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module inst_ram(
    input logic          clk,
    input logic          inst_sram_en,
    input logic          inst_sram_wen,
    input logic  [31: 0] inst_sram_addr,
    input logic  [31: 0] inst_sram_wdata,

    output logic [31: 0] inst_sram_rdata
    );
    
    logic [31:0] instr[1023:0]; //1kb

    initial begin
        $readmemh("C:/Users/Tianlin/Desktop/inst_mem.txt",instr);
    end

    assign inst_sram_rdata = instr[inst_sram_addr[11:2]];

endmodule
